Dynamic design of solar cell structures, photovoltaic modules and corresponding processes

ABSTRACT

Photovoltaic modules can be formed with a plurality of solar cells having different sized structures to improve module performance. The sized can be determined dynamically based on estimated properties of the semiconductor so that the current outputs of the cells in the module are more similar to each other. The modules can produce higher power relative to modules with similar equal sized cells that do not produce matched currents. Appropriate dynamic processing methods are described that include processing steps that provide adjustments of the processing according to the dynamic adjustments in cell designs.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority to U.S. provisional patent applicationSer. No. 60/902,006 filed Feb. 16, 2007 to Hieslmair, entitled“Photovoltaic Cell Structures, Solar Panels and CorrespondingProcesses,” incorporated herein by reference.

FIELD OF THE INVENTION

The invention relates to photovoltaic cells, photovoltaic modules andprocesses for the formation of these devices in which processingparameters are selected dynamically based on semiconductor propertymeasurements. In some embodiments, the invention relates to rear pointcontacted photovoltaic cells and corresponding modules, which maycomprise thin films of silicon/germanium semiconductor material.

BACKGROUND OF THE INVENTION

Various technologies are available for the formation of photovoltaiccells, e.g., solar cells. A majority of commercial photovoltaic cellsare based on silicon. With non-renewable energy sources continuing toincrease in price, there is continuing interest in alternative energysources. Increased commercialization of alternative energy sourcesrelies on increasing cost effectiveness through lower costs per energyunit, which can be achieved through improved efficiency of the energysource and/or through cost reduction for materials and processing.

Photovoltaic cells operate through the absorption of light to formelectron-hole pairs. A semiconductor material can be conveniently usedto absorb the light with a resulting charge separation. Current isharvested at a voltage differential to perform useful work in anexternal circuit, either directly or following storage with anappropriate energy storage device.

SUMMARY OF THE INVENTION

In a first aspect, the invention pertains to a photovoltaic modulecomprising a transparent substrate and a plurality of series-connectedsolar cells attached to the transparent substrate. In some embodiments,the area of at least two cells are different from each other, and thedifference in area of the cells results in a better match of currentoutput of the individual cells relative to cells of equal area with thesame respective photo-conversion efficiency as the particular cells ofthe module.

In a further aspect, the invention pertains to a solar cell comprising asemiconductor sheet having a front surface configured to receive lightand a rear surface opposite the front surface, p-dopant regions andn-dopant regions located along the rear surface, and two electricalinterconnects providing respectively electrical contact between thep-dopant regions and the n-dopant regions. In some embodiments, thep-dopant regions and the n-dopant regions are not symmetrically locatedalong the rear surface.

In another aspect, the invention pertains to a method for subdividing asemiconductor sheet for use as individual photovoltaic cells within aphotovoltaic module. The method can comprise cutting the semiconductorsheet into unequal area subsections based on measurements along thesemiconductor sheets. The measurements can be correlated with expectedcurrent generated for an area of the semiconductor material at themeasured location.

In additional aspects, the invention pertains to a method for producinga solar cell comprising depositing dopants in association with asemiconductor layer in an un-symmetric pattern based on performancemeasurements for semiconductor layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic side perspective view of a photovoltaic modulewith a portion of the backing layer removed to expose some of the solarcells within the module.

FIG. 2 is a sectional side view of the photovoltaic module of FIG. 1taken along line 2-2 of FIG. 1.

FIG. 3 is a bottom view of a photovoltaic module with the backing layerremoved to expose the solar cells within the module.

FIG. 4 is a bottom perspective view of an individual solar cell.

FIG. 5 is a sectional view of the solar cell of FIG. 5 taken along line5-5 of FIG. 4.

FIG. 6 is a bottom view of a semiconductor substrate with the currentcollectors removed to expose dopant domains through holes drilledthrough a passivation layer.

FIG. 7 is a bottom view of an alternative embodiment of a solar cell.

FIG. 8 is a bottom view of the solar cell of FIG. 7 prior to applicationwith the current collectors removed to expose dopant domains withinholes through a passivation layer.

FIG. 9 is a flow diagram indicating the process of module preparation,although the particular steps can have sub-steps that are performed in adifferent order relative to the overall process of the flow diagram.

FIG. 10A is a bottom view of a semiconductor sheet with a dynamic cellselection indicated.

FIG. 10B is a bottom view of the sheet of FIG. 10A following the cuttingof the cells and the drilling of holes for dopant placement.

FIG. 11 is a bottom view of a semiconductor sheet showing cut cell afterreal time cell selection.

FIG. 12 is a flow diagram indicating steps for solar cell processing,although the order shown in the diagram is not necessarily theprocessing order.

DETAILED DESCRIPTION OF THE INVENTION

Dynamic processing approaches described herein for forming photovoltaicmodules can provide more efficient solar cells and correspondingphotovoltaic modules that produce higher power for a relatively fixedamount of materials within the module. In particular, photovoltaicmodules can be formed from larger sheets of semiconductor material thatcan be measured to map out the expected performance characteristicsacross the sheet. The measurements of anticipated performance propertiesof the semiconductor material provide a basis for the dynamic processingof the semiconductor. In some embodiments, processing approaches aredirected to the formation of electrically connected photovoltaic cellswith rear connections. The improved processes are suitable for thinsemiconductor film processing, although the approaches can also be usedfor thicker semiconductor layer processing.

Some of the processing improvements described herein are particularlysuitable for module level processing of a plurality of cellssimultaneously. Doping approaches described herein are suitable for realtime selection of dopant placement. Through the inspection of thesemiconductor material and real time dopant deposition, the individualcell size and location can be selected to produce similar currents sothat the overall power generation of the module can be improved. Thesepower improvement approaches and corresponding processing steps cangenerally be used for any type of solar cell using a range ofsemiconductor materials.

Photovoltaic modules generally comprise a transparent front sheet thatis exposed to sunlight during use of the module. The solar cells, i.e.,photovoltaic cells, within the photovoltaic module can be placedadjacent to the transparent front sheet such that light transmittedthrough the transparent front sheet can be absorbed by a semiconductormaterial in the solar cell. The transparent front sheet can providesupport, physical protection as well as protection from environmentalcontaminants and the like. The photovoltaic cells are generallyconnected in series to increase the available voltage of the module. Aphotovoltaic module can comprise sets of connected parallel photovoltaiccells along with the sets of cells connected in series. The activematerial of a photovoltaic cell is generally a semiconductor. Followingabsorption of light, photocurrent can be harvested from the conductionband to perform useful work through connection to an external circuit.

Doped contact regions interfacing with the semiconductor materialfacilitate the harvesting of the photocurrent. In particular, electronicand holes can segregate to the respective n+-doped and p+-doped regions.The doped-contact regions interface with electrical conductors to formcurrent collectors to harvest the photocurrent formed by absorbing lightto generate a potential between the two poles of the contacts. Within asingle cell, the doped contact regions of like polarity are connected toa common current collector, such that the two current collectorsassociated with the different polarities of doped contacts form thecounter electrodes of the photovoltaic cell.

While the voltages are additive for solar cells connected in series, thecurrent of the series of cells depends on the performance of theindividual solar cells. In particular, the current through the series ofcells is essentially the current capability of the poorest currentdelivering solar cell in the series since the weakest solar cell cannotsupport a higher current at a common illumination level. Power availablefrom higher performance cells is lost trying to push current through thelower performing cells. The power from series connected solar cells isthe product of the current times the voltage of the unit. The current ofa particular cell can be a function of the carrier lifetime, which isrelated to the efficiency for harvesting current from populatedconduction bands upon absorption of light. Generally, the efficiency ofthe cell is also related to the design of the cell, for example, withrespect to division of the cell into p+-doped and n+-doped regions andplacement of the doped regions.

In some embodiments of improved modules described herein, the size ofthe individual cells can be sized based on measured properties of thesemiconductor material that is formed into the photovoltaic cells. Thus,the collection of cells for a module can be selected to havesignificantly smaller differences in current capabilities relative tocorresponding cells cut with equal size. This selection of cell areascan be particularly convenient when the individual cells are divided orcut from a larger sheet so that the area of the sheet can be effectivelyand appropriately divided. Specifically, a semiconductor sheet can beevaluated to estimate minority carrier lifetimes, which is the primarydeterminant of performance, at selected locations along the surface ofthe semiconductor. In general, the measurements of the semiconductorproperties can be performed before or after formation of p-doped and/orn-doped contacts, although dopant contact placement can also beperformed dynamically if the measurements are performed prior to dopantdeposition. These estimates can provide the basis for dividing the totalarea of the semiconductor material into more even current generatingcells with unequal sizes. The size of the cells can be selected based onthe real time measurements in a dynamic rather than static process. Thecut cells can then be assembled into a single photovoltaic module, aplurality of modules or a portion of a module.

The placement of dopant contact regions within a cell influencesperformance of a cell. In particular, the spacing of p+-doped regionswith respect to n+-doped regions as well as the size of the dopedregions can influence cell performance. Similarly, the area attributedto differently doped contact regions, i.e., p+-doped and n+-dopedregions, can be balanced based on estimated performance propertiesacross the cell. Thus, the number and/or placement and/or size ofn+-doped regions and p+-doped regions can be selected to improve currentgeneration efficiency of an individual cell. The ability to select thenumber and/or placement and/or size of doped contact regions within anindividual cell is based upon the ability to selectively deposit thedopants in real time based on the dynamic evaluation of the desireddopant locations. Using real time evaluation, the individual cells canbe designed dynamically rather than statically as an alternative oraddition to dynamic selection of overall solar cell sizes. Theprocessing approach generally can also influence the placement and sizeof the doped regions at least with respect to available ranges.

Generally, the dynamic processing approaches described herein can beapplied for photovoltaic structures based on any type of semiconductormaterial, such single crystalline silicon, polycrystalline silicon,amorphous silicon, cadmium selenide, cadmium telluride, CIS alloys andthe like. CIS alloys refer to chalcogenide alloys generally involvingCu, In, Ga, Se and S. The semiconductor sheets generally can be doped toincrease charge mobility, although the overall dopant levels across thesemiconductor layer are less than the dopant levels of appropriatecorresponding doped contacts.

In the following, embodiments of particular interest based onpolycrystalline silicon are discussed in more detail, althoughappropriate portions can be generalized for other semiconductor systemsbased on the disclosure herein. Furthermore, thin silicon films can besuitable for dynamic processing in which the films have a thickness formabout 5 microns to about 100 microns. These thin films make effectiveuse of materials while providing an efficient format for subdividing thefilms according to the approaches described herein to improve output ofcells and modules. The formation of these thin films is made possible asa result of revolutionary process approaches described further below.

In embodiments of particular interest, the photovoltaic module comprisesa silicon, germanium or silicon-germanium alloy material that is usedfor the semiconductor substrate. For simplicity of discussion, thereference in the specification to silicon implicitly refers to silicon,germanium, silicon-germanium alloys and blends thereof, unless indicatedotherwise in context. In the claims, silicon/germanium refers tosilicon, germanium, silicon-germanium alloys and blends thereof.

Metal or other electrically conducting material connects to the dopedsemiconductor regions as a current collector within a cell. The currentcollectors of adjacent cells can be joined with electrical connectionsto connect the cells in series. The end cells in the series can beconnected to an outside circuit to power selected applications or tocharge an electrical storage device, such as a rechargeable battery. Thephotovoltaic module can be mounted on a suitable frame.

In general, a photovoltaic cell comprises a photoconductingsemiconductor structure with a front surface designed for receivinglight. The front surface may have an antireflective coating and/or atexture or the like. The front surface generally is designed forplacement adjacent a transparent layer, such as a silica glass layer,within a photovoltaic module. The rear surface of the cell faces awayfrom the transparent front sheet, and generally provides for at leastsome of the electrical connections to the cell. The module generally canhave a rear seal, which may function together with a front transparentmaterial and/or frame, to protect the solar cells in the photovoltaicmodule from moisture and other environmental contaminants. Appropriateelectrical connections extend from the sealed module.

The semiconductor doped regions can be formed as doped domains along thesemiconducting material, in which the doped domains can extend into thesemiconductor material and/or extend from the surface of thesemiconductor material. Various contact structures have been designedfor photovoltaic cells. For example, some cells have one type of dopedregion on the front surface and a second type of doped region on therear surface. Generally, any front placed doped regions need to be inelectrical contact with a current collector that extends to connect thecontact with the opposite pole of an adjacent cell for a seriesconnection or to an external circuit. In some embodiments, each cell hasdoped regions of opposite polarity both along the rear or back side ofthe cell. Placement of the doped regions of both polarities on the rearsurface can provide convenient processing while less processing isdirected to the front surface. For rear connected solar cells, the frontsurface can be free of structures that may interfere with access toirradiation of the semiconductor material with light.

P+-doped regions generally comprise an electron deficient dopant, suchas B, Al, Ga, In or combinations thereof. N+-doped regions generallycomprise an electron rich dopant, such as P, As, Sb, or combinationsthereof. The p+-doped regions form the cell anode (emitter), and then+-doped regions form the cell cathode (collector). In some embodiments,the rear side of the cell has a plurality of p+-doped regions and aplurality of n+-doped regions. In some embodiments, the front and/orrear sides of the semiconducting material can comprise a passivationlayer that is electrically insulating. Suitable materials to formpassivation layers include, for example, stoichiometric and nonstoichiometric silicon oxides, silicon nitrides, and siliconoxynitrides, with or without hydrogen additions.

For the dynamic module and cell processing described herein, real timemeasurements can be used to estimate performance characteristics, suchas carrier lifetimes, at different physical locations along thesemiconductor material. The measurements can be made, for example, usingnon-destructive optical techniques, which can provide for rapidevaluation of the semiconductor material in relatively large sheets. Theoptical measurements can be made at selected resolution, and furtherextrapolation and interpolation can supplement the direct measurements.The measurements can then be used to select cell sizes and/or dopantplacement to improve the efficiency of the resulting cells and modulesthrough improved matching of current performance. However, to takeadvantage of these measurements, corresponding efficient techniques tocut the semiconductor and/or place dopants along the semiconductor canbe implemented in real time adjustable procedures based on themeasurements.

In some embodiments, a plurality of solar cells is cut from a largersheet of semiconductor material. Generally, any reasonable cuttingapproach can be used. For example, mechanical cutting, fluid jet cuttingor radiation based cutting can be used to cut the larger sheet. In someembodiments, radiation-based cutting, such as with a laser, can beeffectively used to make sharp divisions to form individual cells. Thesemiconductor sheet can be supported on a substrate during the cuttingprocess. It can be particularly desirable to support the semiconductorsheet for embodiments in which the semiconductor is a thin foil, suchthat the cut sections are less likely to suffer damage in handling.

The cut segments may or may not be repositioned with respect toplacement within a photovoltaic module. In other words, in someembodiments, the original semiconductor sheet can be selected to providethe semiconductor structure for a photovoltaic module or a selectedportion thereof, and the semiconductor sheet is then subdivided intoindividual cell through the cutting process. For example, thesemiconductor sheet or a plurality of semiconductor sheets, can besecured to the transparent front sheet of the module for cutting suchthat the cut cells structures are appropriately positioned for furtherprocessing into the complete module without changing the position of thesemiconductor material on the transparent front sheet. In alternativeembodiments, the cut semiconductor sections cut form a single sheet canbe separately assembled into a plurality of modules, such as one portionof segments being assembled into a first module and another portion ofsegments being assembled into a second module. In further embodiments,the cut segments can be assembled with segments cut from one or moreother semiconductor sheets into a single module, or the cut segments canbe combined with cut segments from other semiconductor sheets forassembly into multiple modules.

In general, dopants can be applied in any reasonable process to thesemiconductor materials to form doped contacts. For example, a liquidcomposition comprising a dopant element can be deposited forincorporation into the semiconductor. Alternatively, approaches havebeen described for obtaining dopants from doped silicon oxide particlesto transfer to a silicon substrate. In further embodiments, dopedsilicon particles can be used to form doped silicon domains associatedwith the semiconductor sheet. These approaches are discussed furtherbelow in the context of printing approaches for the doping of thinsilicon/germanium foils.

For the deposition of dopants for photovoltaics, the resolutiongenerally is intermediate in the sense of having a micron scaleresolution, but not on the even smaller scale of current integratedcircuit components. Thus, inkjet printing, other printing approaches orthe like can be convenient to deposit a liquid dopant composition atselect locations along the cell, such as along the rear or backside ofthe cell, to provide dopant atoms to subsequently form the respectiven+-doped and p+-doped domains. While conventional inkjet heads can beadapted for this use, redesigned print heads for the specificapplication can similarly be used to deliver desired volumes of liquidfrom a reservoir at dynamically selected locations.

An inkjet process introduces a great level of flexibility to theprocessing of the doped contact regions. Specifically, the dopingprocess can be dynamically adjusted in a straightforward way for aparticular semiconductor sheet. Thus, based on measurements for theparticular semiconductor sheet, the location of the doped regions can beselected. As noted above, the size of individual cells can be selectedbased on semiconductor properties across the surface of thesemiconductor sheet. If the cell sizes are selected based onsemiconductor measurements, based on the selected sizes of the cells,the dopant domains can be correspondingly selected to fit within theparticular cell size and shape. Furthermore, dopant placement can beselected based on semiconductor measurements even if the cell size isnot dynamically selected, i.e., if the cells are formed to be of equalsize. Similarly, the dopant placement as well as the size and/or dopantlevels of individual doped contacts can be also selected if desiredbased on measurements relating to the semiconductor properties. Usingthe deposition approaches described herein, dopant inks or other dopantformulations can be printed or deposited at the selected locations inreal time for rapid and efficient processing.

In general, any composition suitable for delivering dopant atoms in anink form can be incorporated into the ink. Inks are considered broadlyas a liquid composition capable of providing the desired dopantelements. In particular, nanoscale particles dispersed at relativelyhigh concentrations can be used in dopant inks. Dopant inks can compriseparticles with selected compositions to deliver desired dopants atdesired concentrations. For example, highly doped silica particlesand/or silicon particles can provide the dopants without introducing anysignificant quantities of contaminants with respect to silicon-basedsemiconductor sheets. In other embodiments, dopant inks can comprisenon-particulate dopant compositions.

In appropriate embodiments, the doped particles for forming the inks canbe synthesized through any appropriate process. However, highly dopedparticles can be produced with desirable properties, for example, usinglaser pyrolysis, which is a convenient and versatile approach for thesynthesis of highly uniform submicron particles with a range ofselectable dopants. While in principle a range of doped particles aresuitable, doped submicron particles or nanoparticles having an averageprimary particle diameter no more than about 250 nm are desirable due totheir ability to form good dispersions. In some embodiments, the dopedparticles comprise Si, Ge, SiO₂, GeO₂, combinations thereof, alloysthereof or mixtures thereof. Doped particles may be surface modifiedwith associated compositions to stabilize the particle dispersions.

As noted above, various dopant configurations and cell designs can beused for the solar cell structure, such as dopant contacts along boththe front and rear cell surfaces. Similarly, any reasonable combinationof processing approaches can be adapted for dopant placement withrespect to selected dopant locations on the semiconductor substrate. Thefinal cell structure can include other layers in addition to atransparent front sheet, a semiconductor sheet, current collectors anddopant regions. These additional layers can include, for example,adhesive layers, dielectric layers, antireflective layers, protectivelayers and the like. General approaches are described further below forgeneral placement of dopant and contact structures. However, a moredetailed description is provided for a particular embodiment relating toa silicon foil semiconductor in which dopants are deposited along therear surface and all contacts are correspondingly placed along the rearsurface of the cell.

In some embodiments, for the formation of a rear contact solar cell,efficient processing can be achieved from the deposition of apassivation, dielectric layer onto the semiconductor rear surface priorto introducing the dopant for the semiconductor layer. Then, portions ofthe passivation layer can be removed to expose the semiconductor surfaceto allow for contact with the dopant. Openings/holes can be placedthrough the passivation layer, for example, using a laser or the like,although other approaches, such as mechanical drilling or etching can bealternative or additional approaches. Laser drilling or other approachescan be controlled to expose the semiconductor surface withoutsignificantly damaging the semiconductor surface. The size of the holes,the number of holes and/or placement of the holes can be selected toyield desired degrees of doping and cell performance.

In general, there are multiple dopant locations of opposite polarityacross a particular cell. If the sizes of the individual cells aredynamically selected, the size of a particular cell can directlyinfluence the number and placement of doped contacts. Also, thecorresponding placement of the doped regions can be based onmeasurements of the semiconductor properties across a particular cell sothat the performance associated with n+-doped contacts and p+-dopedcontacts are balanced such that improved current output of the cell canbe realized relative to purely geometric placement of doped-contacts.The dopant locations can be selected to yield high efficiency of currentharvesting as long as reasonable approaches are available for formingcurrent collectors. Thus, doped-contact placement should also accountfor appropriate placement of current collectors based on the selectedprocess for current collector placement. With respect to thecoordination of processing steps, placement of holes through apassivation layer can be based upon on the selected pattern of placementof the doped domains along the semiconductor surface.

In some embodiments, patterned layered structures can be used to formdesired current collector configurations. The use of lithography,photolithography or the like can be adapted to form the layered currentcollector structures. However, printing approaches can also be used toform current collectors which are consistent with dynamic selection ofthe placement of dopant portions of the cell contacts thatcorrespondingly result in the need to dynamically place the electricalinterconnects such that the current collectors connect the dopantregions of common polarity. In general, the use of a reasonably largenumber of dopant domains can be desirable since then the p-doped andn-doped regions can have a shorter distance to an adjacent doped region.If adjacent doped regions are close to each other more efficientharvesting of the photocurrent can take place.

After a dopant ink is deposited at selected positions along thesemiconductor surface, the dopants can be further processed to form thedoped contact. For dopant compositions and doped silicon oxideparticles, the dopants generally are driven into the layer ofsemiconductor material at the deposited locations, such as throughheating of the structure in an oven to mobilize the dopants, which thenmigrate into the semiconductor material. The diffusion of the dopantatoms depends on the time and diffusion conditions. In general, the ovenbased approach is relatively slow and tends to drive the dopantsrelatively deeply into the semiconductor material in order to obtaindesired levels of dopant within the semiconductor.

Alternatively or additionally, dopants can be driven into thesemiconductor using an intense light source. For example, a laser beamcan be pulsed onto the surface to melt a very thin layer along thesurface to form a doped region. In particular, a laser can provide anintense pulse over a relatively large area to process the dopant intothe surface. Generally, suitable lasers can emit light with wavelengthsranging from infrared to ultraviolet. The pulsing of the laser can berepeated to achieve the desired level of dopant drive into the surface.If silicon oxide particles are used to provide the dopant atoms, afterthe dopant is driven into the semiconductor, the remnants of theparticles from the dopant ink can be removed from the surface through anappropriate etching process. In some embodiments, this can be donewithout removing the passivation layer.

For embodiments in which silicon particles are used to deliver thedopant atoms to the doped regions, the silicon particles can be fused atthe location to directly form the doped regions. Some dopant may or maynot diffuse into the underlying silicon sheet during this fusingprocess. Thus, the resulting doped contact region can be in the form ofa thin island on top of the semiconductor sheet and/or within thesurface of the semiconductor sheet. In either case, efficient harvestingof the photocurrent can take place since a thin doped contact over thesemiconductor sheet can perform similarly to a contact within thesemiconductor sheet.

Once the p+-doped regions and n+-doped regions are formed throughappropriate doping, the doped regions of like polarity are connected torespective current collectors. In appropriate embodiments, the holesthrough the passivation layer can be used to form the electricalconnection with the doped domains. Various approaches can be used todeposit the current collector material. For example, the currentcollector can be formed using a silver ink that is deposited at theappropriate locations, such as with an inkjet or screen printing.Suitable commercial silver inks include, for example, DowCorning® Brandhighly conductive silver inks and conductive silver ink 2512 fromMetech, Elverson, Pa. Alternatively or additionally, physical vapordeposition or the like can be used to deposit the current collectormaterial. Following deposition of the current collector material, thestructure can be heated to crosslink, fuse and/or anneal the currentcollector material if appropriate. In some embodiments, a seed layer canbe deposited for the current collector and electrochemical deposition isused to complete the current collector formation.

The current collectors generally should be connected to link adjacentcells in series. To accomplish this objective, the current collectormaterial can be deposited in a configuration that extends to connect thecells over an electrically resistive bridge or the like and/oradditional wiring or the like can be used to connect the currentcollectors of adjacent cells. An adhesive and/or backing material can beplaced over the cell rear surface to protect the rear surface and tofacilitate handling. Specifically, a backing structure, such as apolymer sheet can be placed over the entire back and/or sides of themodule. The cell module can be placed into an appropriate frame eitherbefore or after placement of a backing material or the like. Electricalleads for positive and negative poles should be accessible forconnection to an external circuit following completion of the module,although leads can be covered or otherwise protected for shipping and/orstorage.

The ability to dynamically process solar cells and corresponding modulesin real time provides the ability to improve module performance for agiven amount of material to improve, i.e., reduce, average cost per unitof power generation. Correspondingly, the uniformity of the modules canbe improved since variation within a semiconductor sheet can beaccounted for in the cell processing such that a module performs closerto the specification of the average semiconductor sheet. Thus, oneaspect of process variation can be reduced. In general, appropriatedoping approaches provide for convenient real time programming of dopantplacement that allows for adjustment of cell size based on semiconductormeasurements to improve further the module performance and potentiallythe performance of individual cells. In some embodiments, convenientprocessing approaches comprise a relatively early in the processassociation of the cells with the transparent front sheet withadditional processing taking place along the rear of the cell.

Module and Cell Structures

The photovoltaic modules generally have a transparent front sheet and aprotective backing layer with the solar cells between the transparentfront sheet and the protective backing layer. A plurality of solar cellsgenerally is connected in series within a photovoltaic module. Thesemiconductor structure of the photovoltaic cell can be a thin siliconfoil, although the processing approaches herein can be applied for othersemiconductor materials and formats. Each cell generally has a pluralityof doped domains to form the contacts for the two polarity currentcollectors of the cell. In some embodiments, the solar cells can be rearor back surface contact solar cells, although other contact structurescan be adopted in further embodiments. High cell performance can beexpected from the structures described herein.

A schematic view of a photovoltaic module is shown in FIG. 1.Photovoltaic module 100 can comprise a transparent front sheet 102, aprotective backing layer 104, a protective seal 106, a plurality ofphotovoltaic cells 108 and terminals 110, 112. A sectional view is shownin FIG. 2. Transparent front sheet 102 can be a sheet of silica glass orother suitable material that is transparent to appropriate sun lightwavelengths and provides a reasonable barrier to environmental assaultssuch as moisture. Suitable materials for the module components arediscussed in more detail in the following section. Backing layer 104 canbe any suitable material that provides protection and reasonablehandling of the module at an appropriate cost. Backing layer 104 doesnot need to be transparent and in some embodiments can be reflective toreflect the light that transmitted through the semiconductor backthrough the semiconductor layer where a portion of the reflected lightcan be adsorbed. Protective seal 106 can form a seal between frontprotective sheet 102 and protective backing layer 104. In someembodiments, a single material, such as a heat sealable polymer film,can be used to form backing layer 104 and seal 106 as a unitarystructure.

Solar cells 108 are placed with their front surface against transparentfront sheet 102 so that solar light can reach the semiconductor materialof the photovoltaic cells. Solar cells can be connected electrically inseries using current collectors 120, conductive wires or the like. Endcells in the series can be connected respectively to terminals 110, 112that provide for connection of the module to an external circuit. Insome embodiments, some solar cells can be connected in parallel toincrease the current with an offsetting decrease in voltage, and/or setsof series connected photovoltaic cells can be connected to separateterminal associated with a large module if each series of cellsgenerates an appropriate amount of voltage. Furthermore, the averagesize of each photovoltaic cell can be adjusted to achieve desired moduleproperties. For example, the formation of a module with fewer, largercells connected in series generate a relatively larger amount of currentat a lower voltage relative to a larger number of smaller cells over thesame module footprint. The voltage from the series of cells isdetermined by adding the individual voltages of the individual seriesconnected cells.

A particular intended application generally influences the selection ofmodule size. For example, potential applications range from smallindividual external lights to solar panels for a residential house topanels for a commercial scale electricity generation facility.Reasonable module sizes may range, for example, from four squarecentimeters (cm²) or less to several square meters or larger. Once theoverall size is selected for a module, the average individual cell sizescan be selected to balance current versus voltage as well as processingconsiderations and material considerations. The dynamic processingapproaches herein can be adapted for any of these selected embodimentswith appropriate corresponding equipment design. In some embodiments,the module comprises at least 10 cells, in further embodiments at least20 cells and in additional embodiments from about 24 cells to about 200cells. A person of ordinary skill in the art will recognize thatadditional ranges of cell number within the explicit ranges above arecontemplated and are within the present disclosure.

A bottom view of an embodiment of a photovoltaic module 130 is shown inFIG. 3 with the backing layer removed. In this embodiment, photovoltaiccells 132 with different areas are mounted on transparent front sheet134. In some embodiments, an entire collection of cells in a module iscut from a single large semiconductor sheet, or a set of cells of themodule is cut from a single semiconductor sheet. Dynamic cell cuttingand doping processes allow for efficient selection of cells with areasbetter matched for current generation. As shown in FIG. 3, the pluralityof cells is cut with approximately the same cell width while the celllengths are selected to adjust current generation of the cell to aselected value. Other formats of cell division can be used as describedfurther below.

Referring to FIGS. 4 and 5, an embodiment of an individual photovoltaiccell is shown. In some embodiments, photovoltaic cell 150 can comprise asemiconductor layer 152, a front surface passivation layer 154, a rearsurface passivation layer 156, negative contact or collector 160, andpositive contact or emitter 162. Collector 160 generally is inelectrical contact with n+-doped regions 164, as shown in the crosssectional view in FIG. 5. Emitter 162 generally is in electrical contactwith p+-doped regions 166, as shown in FIG. 5. Doped regions 164, 166can be positioned below holes 168 in passivation layer 156, and holes168 can be filed with current collector material to make electricalcontact with doped regions 164, 166.

A bottom view is shown in FIG. 6 of the solar cell with the currentcollector material removed. In general, doped regions and correspondingholes or openings through the passivation layer can have any reasonableshape that separates the different poles of the cell. For example, theholes/openings through the passivation layer can have generallycylindrical shapes, groove shapes or other desired shapes. Roughlycylindrical holes can be formed conveniently using the processesdescribed herein. For example, the holes can be formed by laserdrilling. Similarly, openings shaped as grooves can be formed byappropriately moving a laser beam between pulses. If a greater amount ofpassivation material is removed, the corresponding size of the dopedregions increases. Thus, if more passivation material is removed,contact resistance may decrease but surface recombination of holes andelectrons may increase so that a balance between these effects caninfluence cell design.

In general, the holes can have average diameters, with averages overdifferent holes as well as over non-circular shapes, ranging form 5microns to about 100 microns and in further embodiments from about 10microns to about 30 microns. The spacing of the holes can be from about50 microns to about 500 microns and in further embodiments from about 80microns to about 240 microns. A person of ordinary skill in the art willrecognize that additional ranges of hole dimensions and spacing withinthe explicit ranges above are contemplated and are within the presentdisclosure.

Alternating rows are visible of n+-doped regions 164 and p+-dopedregions 166 within holes 168 through layer 156. To simplify the diagram,only two rows are labeled with reference numbers 164, 166, but it isclear how these contacts line up with current collector strips in FIG. 4so that n+-doped regions are in electrical contact with negative currentcollector 160, and p+-doped regions are in electrical contact with thepositive current collector 162. Similarly, only two example holes arelabeled in the figure, although each doped region is associated with ahole. While the holes are shown in a rectangular grid in FIG. 4, thehole placement can be performed based on semiconductor propertymeasurements across the surface such that the hole placement isdynamically determined for a particular structure with placementconstrained by the ability to form appropriate current collectors.

An alternative embodiment of a solar cell is shown in FIGS. 7 and 8. Inthis embodiment, photovoltaic cell 178 has n+-doped regions 180 andp+-doped regions 182 that are arranged in a checkerboard fashion, asshown in FIG. 8. Negative contact 184 and positive contact 186 arecorrespondingly aligned in angled stripes as shown in FIG. 7. Then,negative contact 184 is in electrical contact with n+-doped regions 180,and positive contact 186 is in electrical contact with p+-doped regions182. While FIGS. 6 and 8 depict geometrically arranged contacts, thedynamic selection of contact placement can involve less symmetricplacement of the contacts, as described further below.

The structure in FIG. 7 has the current collector material for the twopoles deposited as a common level on the structure. For a rear contactphotovoltaic cell, two layer current collector structures with aninsulating layer separating the opposite polarity electrodes have beendescribed. See, U.S. Pat. No. 4,927,770 to Swanson, entitled “Method ofFabricating Back Surface Point Contact Solar Cells,” and U.S. Pat. No.6,423,568 to Verlinden et al., entitled “Method of Fabricating a SiliconSolar Cell,” both of which are incorporated herein by reference. Whilethe two layer current collector structure can be incorporated into thestructures described herein, a two layered structure would addprocessing steps.

Regardless of the configuration of the metal fingers, the metal fingersand associated metal surface can be designed to cover as much area aspractical without having the opposite poles touching since the metalalso functions as a rear light reflector. Thus, the finger width can beapproximately at least about 40 percent of the finger pitch, i.e.,spacing between centers of the fingers, and in further embodiments atleast about 50 percent of the finger pitch and in additional embodimentsfrom about 60 to about 85 percent of the finger pitch. A person ofordinary skill in the art will recognize that additional ranges offinger pitch within these explicit ranges are contemplated and arewithin the present disclosure.

The discussion above focuses on thin film semiconductor solar cells withrear contacts. However, the dynamic processing aspects with respect tocell size and dopant placement can be applied for other cellconfigurations. For example, thin film solar cells with a combination offront and rear contacts are described further in U.S. Pat. No. 6,455,347to Hiraishi et al., entitled “Method of Fabricating Thin-FilmPhotovoltaic Module,” incorporated herein by reference. Anotherrepresentative photovoltaic module structure with front contacts andrear contacts is described in U.S. Pat. No. 5,956,572 to Kidoguchi etal., entitled “Method of Fabricating Integrated Thin Film Solar Cells,”incorporated herein by reference. The dynamic processes described hereincan be adapted for processing cells with both front contacts and rearcontacts based on the teachings herein. For these embodiments, thedynamic cutting of the cells can be performed prior to the transfer ofthe semiconductor sheet to the transparent front sheet such that thefront surface of the semiconductor layer can be processed with respectto placement of the front surface contacts prior to securing the cellsto the transparent front surface. After securing the cells to thetransparent substrate, the remainder of the processing can be performedwith respect to the rear surface. Suitable solar cell structures withrear contacts are described further in copending U.S. patent applicationSer. No. 12/______, filed on the same date as the present application,to Hieslmair et al., entitled “Solar Cell Structures, PhotovoltaicPanels and Corresponding Processes,” incorporated herein by reference.

Materials for Photovoltaic Assemblies

Examples of suitable materials for incorporation into the photovoltaicmodules are described in the following. The transparent front sheet canbe, for example, a silica glass, other inorganic glass material, atransparent polymer material, composites thereof or the like. Thetransparent front sheet can have an antireflective coating or otheroptical coating one or both surfaces. Suitable polymeric backing layersinclude, for example, Tedlar® “S” type, a polyvinyl fluoride film, fromDuPont. With respect to reflective materials, the polymer sheet for thebacking layer can be coated with a thin metal film, such as metalizedMylar® polyester film. A protective seal joining the transparent frontsheet and a backing layer can be formed from an adhesive, a natural orsynthetic rubber or other polymer or the like.

In general, any reasonable semiconductor material useful for solar cellscan be processed as described herein if the material can be formed intosheets that can be appropriately cut into selected cell sizes. However,polycrystalline silicon provides desired levels of performance whilehaving reasonably cost materials available for forming large areasemiconductor sheets that can be cut into individual solar cells. Inparticular, suitable semiconducting material includes, for example, thinfoils of polycrystalline silicon.

Thin foils of silicon or other inorganic semiconductors can be formed ona sacrificial release layer. In some embodiments, the release layer ismechanically weak so that the release layer can be fractured withoutdamage to the silicon layer on top of the release layer. The formationof thin sheets of silicon by Light Reactive Deposition (LRD™) isdescribed further in published U.S. patent application 2007/0212510A toHieslmair et al., filed on Mar. 13, 2007, entitled “Thin Silicon orGermanium Sheets and Photovoltaics Formed From Thin Sheets,”incorporated herein by reference. Similarly, the thin films of siliconon a release layer can be formed using a chemical vapor deposition (CVD)approach onto a porous release layer at an atmospheric orsub-atmospheric pressure. The CVD process onto a porous release layer isdescribed further in U.S. provisional patent application Ser. No.61/062,398 to Hieslmair et al., filed on Jan. 25, 2008, entitled“Deposition Onto a Release Layer for Synthesizing Inorganic Foils,”incorporated herein by reference. The properties of the silicon foilscan be improved through an efficient zone melt recrystallization processdesigned for use with thin foils on a release layer as described furtherin copending U.S. provisional patent application Ser. No. 61/062,420filed on Jan. 25, 2008 to Hielsmair et al., entitled “Zone MeltRecrystallization for Thin Silicon Films,” incorporated herein byreference.

The use of a thin silicon foil reduces material usage while promisinggood cell performance. Thin silicon foils generally have thicknessesfrom about 5 microns to about 100 microns. In some embodiments, the thinsilicon sheets can have a thickness of no more than about 100 microns,such as from 5 microns to 100 microns and any subrange within thisrange. A person of ordinary skill in the art will recognize thatadditional ranges of foil thickness within the explicit ranges arecontemplated and are within the present disclosure. With the use of thinsemiconductor foils formed using a sacrificial, release layer, theexposed surface can be cleaned, textured, coated and/or otherwiseprepared and then the thin foil can be separated from an underlyingsubstrate directly onto a transparent substrate. In some embodiments,one or more additional layers, such as a passivation layer, can bedeposited over and/or under the silicon layer.

The silicon foil can be transferred to the transparent front sheet, forexample, using an adhesive composition to adhere the silicon foil orusing electrostatic interaction. Suitable adhesives include, forexample, silicone adhesives or EVA adhesives. Other reasonable adhesivescan be used for other uses in photovoltaic module assembly, such as theadherence of a backing material, attachment to a frame, forming sealswithin the structure and the like. Other polymers, such as rubbers canbe also used in forming seals. Processes and apparatuses for thetransfer of thin inorganic foils to receiving surfaces is describedfurther in copending U.S. provisional patent application Ser. No.61/062,399 filed on Jan. 25, 2008 to Mosso et al., entitled “LayerTransfer for Large Area Inorganic Foils,” incorporated herein byreference.

In some embodiments, the front and rear sides of the semiconductinglayer can comprise a passivation layer that is electrically insulating.Suitable materials to form passivation layers include, for example,stoichiometric and non-stoichiometric silicon oxides, silicon nitrides,and silicon oxynitrides, silicon carbides, silicon carbonitrides,combinations thereof and mixtures thereof, with or without hydrogenadditions. In some embodiments, passivation layers can comprise, forexample, SiN_(x)O_(y), x≦ 4/3 and y≦2, silicon oxide (SiO₂), siliconnitride (Si₃N₄), silicon rich oxide (SiO_(x), x<2), or silicon richnitride (SiN_(x), x< 4/3). The passivation layers can protect thesemiconductor material from environmental degradation, reduce surfacerecombination of holes and electrons, provide structural design featuresand/or assist with some processing steps, as well as provideanti-reflecting properties for front surfaces. In some embodiments,front passivation layer can comprise SiN_(x)O_(y) or other transparentdielectric material. The passivation layer generally is also chemicallyinert so that the cell is more resistant to any environmentalcontaminants.

Passivation layers can be formed in a similar reactive depositionprocess that forms the thin crystalline silicon layer, although thepassivation layers can be formed from other techniques such as CVD orPVD techniques using, for example, commercial deposition apparatuses, orwith Light Reactive Deposition. Light Reactive Deposition (LRD™) isdescribed further in copending U.S. patent application Ser. Nos.09/715,935 to Bi et al., entitled “Coating Formation By ReactiveDeposition,” 10/414,443 to Bi et al., entitled “Coating Formation ByReactive Deposition,” and 11/017,214 to Chiruvolu et al., entitled“Dense Coating Formation By Reactive Deposition,” incorporated herein byreference. The passivation layers can be deposited with plasma CVD orthe like. The passivation layers generally can have a thicknessgenerally from about 10 nanometers (nm) to 200 nm and in furtherembodiments from 30 nm to 180 nm and in further embodiments from 50 nmto 150 nm. A person of ordinary skill in the art will recognize thatadditional ranges of thicknesses within the explicit ranges above arecontemplated and are within the present disclosure.

The front passivation layer and/or rear passivation layer generally canhave texture to scatter light into the semiconductor layer, for example,to increase effective light path and corresponding absorption of thelight. In some embodiments, the textured material can comprise a roughsurface with an average peak to peak distance from about 50 nm to about100 microns. The texture can be introduced during the deposition processto form the passivation layer and/or the texture can be added subsequentto the deposition step.

As noted above, the processing of the semiconductor material into asolar cell involves the delivery of dopant materials for the formationof doped-contacts. In general, any reasonable ink can be used that iscapable of delivering the desired dopant atoms to the exposed silicon.For example, phosphorous or boron containing liquids can be deposited.In particular, suitable inks can comprise, for example, trioctylphosphate, phosphoric acid in ethylene glycol and/or propylene glycol orboric acid in ethylene glycol and/or propylene glycol. In someembodiments, inks loaded with inorganic particles can be deposited toprovide the dopants. For example, the inorganic particles can comprisedoped silica or doped silicon. Doped silica glasses have been used todeliver dopants for photovoltaic cells using photolithographicprocesses. The use of inks with doped particles can provide for printingof the dopants at desired locations, for example using inkjet printing.

In embodiments of particular interest, the doped particles have anaverage primary particle size of no more than about 250 nm, in otherembodiments no more than about 100 nm, in further embodiments no morethan about 50 nm and in additional embodiments no more than about 25 nm.A person of ordinary skill in the art will recognize that additionalranges of particle size within the explicit ranges above arecontemplated and are within the present disclosure. In general, dopedparticles generally can be formed from either reactive flow basedapproaches or solution based approaches. Submicron inorganic particleswith various compositions can be produced by pyrolysis, especially laserpyrolysis, alone or with additional processing. In particular,approaches have been developed for the synthesis of submicron multiplemetal/metalloid oxide composite particles and other complexmetal/metalloid particle compositions as well as doped compositionsthereof. The metals/metalloid elements are introduced into the reactantstream. By appropriately selecting the composition in the reactantstream and the processing conditions, submicron particles incorporatingthe desired metal/metalloid composition stoichiometry optionally withselected dopants can be formed. The synthesis of doped particles withlaser pyrolysis is described further in U.S. Pat. No. 6,849,334 to Homeet al., entitled “Optical Materials and Optical Devices,” incorporatedherein by reference.

In general, the inks can comprise a suitable liquid to form dispersionsof the particles. Suitable liquids to disperse metal oxide and metalloidoxide particles generally can comprise water, alcohols, other organicsolvents and mixtures thereof. The dispersions can have concentrationsfrom low concentrations to about 30 weight or in some embodiments toabout 20 weight percent or greater. Well dispersed particles can have areasonably small secondary particle size indicating that the particlesare not highly agglomerated in the dispersion. The particles can have asurface modification to stabilize the particles dispersion and/or othersurface active agents can be included in the dispersion.

The formation of suitable inks comprising silicon oxide particles forperforming semiconductor doping is described in copending U.S. patentapplication Ser. No. 12/006,459 to Hieslmair et al., filed on Jan. 2,2008, entitled “Silicon/Germanium Oxide Particle Inks, Inkjet Printingand Processes for Doping Semiconductor Substrates,” incorporated hereinby reference. The formation of suitable inks comprising siliconparticles for forming doped semiconductor domains is described furtherin copending U.S. patent application Ser. No. 12/006,453 to Hieslmair etal. filed on Jan. 2, 2008, entitled “Silicon/Germanium Particle Inks,Doped Particles, Printing and Processes for Semiconductor Applications,”incorporated herein by reference. These materials described in thesepatent applications can be applied to the processes described herein.

Cell Processing and Module Processing

The processing steps described here are appropriate and efficient forthe processing of photovoltaic modules with dynamically designed solarcells within the module. In some embodiments, the solar cells aredesigned for fabrication from thin silicon foils as the semiconductingsheet. However, at least some of the processing procedures are generallyapplicable and advantageous for the production of photovoltaic cellswith a silicon sheet of any thickness as well as cells formed from othersemiconductor materials.

The dynamic processing is structured around the measurement of expectedperformance at a distribution of locations across the semiconductorsurface. Then, based on a selected algorithm, the further processing isdesigned dynamically using the performance measurements. This dynamicprocessing can include, for example, selecting the positions for cuttingthe semiconductor sheet into individual solar cells and/or the selectionof the placement of doped-contacts along the cell. Once the design iscompleted, additional processing steps are performed to complete aphotovoltaic module with improved performance relative to modules formedfrom the semiconductor material without the advantage of dynamicprocessing.

In some embodiments, some of the processing steps in the followingdiscussion are directed specifically to the formation of rear sidecontacts for harvesting of current from the cell, although dynamicprocessing can be performed for other cell contact configurations asnoted above. In general, the processing steps can comprise, for example,semiconductor sheet preparation 190, semiconductor measurements 192,dynamic cell design 194, cell structure processing 196 and modulecompletion 198, as shown in FIG. 9. In some embodiments of the overallprocessing approach described herein, the process generally involves theuse of one or more large sheets of semiconductor, e.g., silicon, thatare divided during the process into individual cells based onmeasurements of the semiconductor properties at points across the sheet.In general, the processes can provide for appropriate handling of thematerials as well as efficient processing with reduced waste and reducednumbers of processing steps without sacrificing the quality of moduleperformance.

The semiconductor sheet preparation 190 is directed to the formation ofan initial semiconductor sheet in preparation for performing furtherprocessing to form solar cells from the semiconductor sheet. The initialsemiconductor sheet structure can be formed generally by any suitableapproach. For example, the semiconductor sheet can be cut from a siliconingot. However, in other embodiments, the semiconductor sheet is formedat least in part with a reactive deposition process. Appropriatereactive deposition processes for forming the semiconductor sheets aredescribed above. Through a reactive deposition process, a very thin foilof silicon can be formed for use in the module. Even though the siliconfoil is thin, it can be handled with appropriate transfer techniquesthat avoid damage to the foil. Some steps relating to cell structureprocessing 196 can be performed prior to semiconductor sheet preparation190. For example, a passivation layer can be deposited prior to formingthe semiconductor sheet with the semiconductor sheet being depositedonto the passivation layer.

Similarly, some of the cell structure processing steps 196 may or maynot be performed prior to performing measurements 192 on thesemiconductor sheet. For example, a surface of the semiconductor may beexposed for performing the measurements such that passivation layers maynot placed on both surfaces prior to making the measurements. For theseembodiments, one passivation layer can be placed prior to performing themeasurements of the semiconductor and/or the semiconductor layer can beassociated with a transparent layer prior to performing thesemiconductor measurements. The transparent substrate can providemechanical support for the semiconductor sheet during the subsequentprocessing steps. However, in alternative embodiments, the semiconductormeasurements may be performed after formation of a top passivation layerand bottom passivation layer. One or both of the passivation layers canbe formed as part of the reactive deposition process.

In some embodiments, in the reactive deposition process, the one or morelayers of the structure with a semiconductor layer are formedsequentially onto a release layer. The release layer can have acomposition and/or mechanical properties that provide for fracture orrelease of the structure from the original substrate. Depending onfurther handling of the silicon foil, either the rear surface or thefront surface of the silicon foil can be formed against the releaselayer. In alternative embodiments, the silicon is directly depositedonto the transparent front sheet so that the front surface of the cellis formed onto the transparent front sheet without any need for arelease layer or corresponding transfer. In either orientation, thestructure can be further processed, such as heat treated, whileassociated with the original substrate. While in principle the dopantregions of the cells can be formed through the reactive depositionprocess, efficient and convenient approaches for forming dopant contactsare described herein that provide for electrical connection to the dopedcontacts.

In the reactive deposition process involving a release layer, therelease layer can be deposited onto a substrate, which may be reusable.The release layer can be a porous, particulate ceramic composition thatcan be deposited through a reactive deposition process, and suitablecompositions include, for example, similar compositions as are suitablefor passivation layers. Since the substrates can be reusable, highquality substrates can be used without excessively increasing the cost.In one example of an embodiment, a thin silicon nitride or siliconoxynitride rear passivation layer can be deposited over the releaselayer. Then, a crystalline silicon layer can be deposited over the rearpassivation layer. In some embodiments, a thin front passivation layercan be deposited over the crystalline silicon layer. If a rearpassivation layer is deposited, the measurements of the semiconductorcan be performed prior to separating the structure from the releaselayer. If a front passivation layer is deposited, the measurements ofthe semiconductor layer can be performed on the exposed rear surface ofthe semiconductor after separation from the release layer and optionallyremoval of remnants of the release layer.

Reactive deposition to form silicon foils and passivation layers isdescribed further above in the materials section. In some embodiments,the structure formed by reactive deposition can then be heated toconsolidate the passivation layers and/or to anneal the crystallinesilicon layer and/or otherwise modify the properties of the layers. Animproved method for performing zone melt recrystallization of thinsilicon foils is also referenced above.

Measurements of semiconductor 192 to estimate performance in a solarcell can be based on carrier lifetime evaluation. In particular, thephoto-current generation of a semiconductor material can be estimated asa function of carrier lifetime of the semiconductor. The evaluationgenerally is performed to estimate performance at different positions onthe sheet prior to doping and/or cutting individual cells. Inparticular, the measurements can be performed on a selected grid ofpoints along the semiconductor sheet. Additional values of carrierlifetime can be interpolated and or extrapolated relative to themeasured points using established linear or nonlinear fitting routines.Thus, for convenience, the measurements can be based on a rectangulargrid with a spacing that can be based at least in part on the resolutionof the measurement technique. The area of a segment along the grid canbe set at a resolution of, for example, about 0.0001 mm² to about 400mm² for each grid position along the measurement grid, with the edgespossibly being fragments of a grid area, where these grid divisionscorrespond respectively to about 10 microns to about 20 mm resolutions.A person of ordinary skill in the art will recognize that additionranges of resolution within these explicit ranges are contemplated andare within the present disclosure.

The measuring apparatus and/or the semiconductor sheet can be translatedon a stage or other conveyor system relative to each other to performthe measurements. In some embodiments, optical components can be movedto scan the semiconductor surface. These measurements can be used todetermine cell configuration and corresponding cell contact placement.

In particular, optical techniques can be used to evaluate the carrierdensity and/or carrier lifetimes of the semiconductor. In someembodiments, carrier densities can be used to estimate carrierlifetimes, which is correlated with current generation of the materialas a photoconductor. The optical measurement of minority carrierdiffusion lengths along a map of the semiconductor surface, which can beused to evaluate carrier lifetimes, is described in published U.S.patent application 2007/0126458 A to Shi et al., entitled Methods andSystems for Determining one or More Properties of a Specimen,”incorporated herein by reference. Also, the carrier density can beestimated from infrared lifetime mapping on the semiconductor materialbefore or after formation of a passivation layer. The infrared lifetimescan be measured, for example, with a charge coupled camera operating inthe infrared portions of the spectrum that is used to measure infraredtransmission of the sample. High resolution scans of the material can beobtained quickly. An article by Isenberg et al. describes the use of aninfrared laser and a commercial CCD camera to obtain a resolution downto 30 microns across the surface of the semiconductor material. Thecitation for the Isenberg article is Journal of Applied Physics,93(7):4268-4275 (1 Apr. 2003), entitled “Imaging method for laterallyresolved measurement of minority carrier densities and lifetimes:Measurement principle and first applications,” incorporated herein byreference. An article by Goldschmidt et al. discusses the calculation ofshort-circuit current and open-circuit voltage based on measurements ofcarrier lifetimes. The Goldschmidt article was presented at the 20thEuropean Photovoltaic Solar Energy Conference and Exhibition, 6-10 Jun.2005, Barcelona, Spain, entitled “Predicting Multi-Crystalline SiliconSolar Cell Parameters From Carrier Density Images,” incorporated hereinby reference. An alternative approach for contact-less estimation ofcharge-current performance of silicon material is described in Trupke etal., Applied Physics Letters 87:093503 (2005), entitled“Suns-photoluminescence: Contactless determination of current-voltagecharacteristics of silicon wafers,” incorporated herein by reference.The processes in the Trupke article can be generalized for spatialresolution across the semiconductor surface.

The semiconductor measurements can be used to perform dynamic celldesign 194, see the process steps of FIG. 9. In general, based on themeasurements across the semiconductor surface, a range of algorithms canbe used to layout the resulting cells. In general, the ability tocorrelate initial materials properties with the final cell powercharacteristics allows one to adjust cell sizes, contact spacing/pitch,and even the ‘stringing’ of cells (connecting subsets of cells in seriesand/or parallel) to increase the entire module power production andcompensate for areas of poor performance.

Given a carrier lifetime map of the silicon foil, the cell sizes can beselected such that the output currents of the cells at the anticipatedpeak power point are well matched. A lower carrier lifetime and/orcarrier density measurement correlates with a lower expected current ofthat region at the peak power point per unit area. Thus, the lowercarrier lifetime regions should be made into larger cells compared tothe higher carrier lifetime regions. The proportionality between initialmaterial carrier lifetime and the proper cell area to achieve currentmatching can be determined empirically and need not necessarily belinear. In particular, for a specific solar cell design, measurements ofthe photocurrent from measured domains can be made to determine thefunctional relationship between the material carrier lifetime with thecorresponding photocurrent and voltage. These functional relationshipscan then be used to perform the dynamic cell design.

Since photovoltaic modules are typically installed at a site in seriesand/or in parallel, it is often desirable for modules to have a certainrated current (series) or rated voltage (parallel). Given a carrierlifetime mapping of the silicon foil or other semiconductor material aswell as empirical knowledge of the cell manufacturing process and theresulting cell properties, a scheme can be devised to divide the foilinto cells such that a target current or target voltage at a higherpower is achieved. To achieve a target current, the cells are dividedsuch that each cell produces a current of approximately the targetvalue. Then, the series connected cells of the module produce an overallcurrent approximately equal to the target value. To reach a targetvoltage, the rough voltage value of a cell can be used to select a totalnumber of cells to reach the target value. Then, appropriate division ofthe sheet into cells that add in series to the target value. Setting acurrent and voltage target simultaneously is possible generally bysacrificing some degree of the power performance. In general, throughdynamic processing, the current variation between any two cells in amodule can be reduced to no more than 8 percent relative to the averagecurrent for the cells, and in further embodiments, no more than about 5percent variation in the current under equivalent illumination at themaximum power point for the combined cells. Similarly, the power of themodule with more uniform current generation of the individual cells isroughly higher as the corresponding current increase for the module. Aperson of ordinary skill in the art will recognize that additionalranges of current and power improvement within the explicit ranges aboveare contemplated and are within the present disclosure.

There has been interest in integrating inverters into modules. If suchinverters become commercially viable, then no target voltage or currentis required. In such a situation, the cell sizes, contact pitch, andstringing of cells can be entirely selected for increased powergeneration. The integrated inverter can condition the module poweroutput into a standard 120V 60 Hz output (US) that can feed directlyinto the power line, or into other standard electrical outputs asselected.

As a representative example, consider the division of the semiconductorsubstrate into one or more stripes. As shown in FIG. 10A, substrate 220is shown with a line 224 indicating the eventual division of the sheetinto two stripes 226, 228. The position of line 224 can be based on theestimated total current from each stripe. As a hypothetic example basedon the embodiment shown in FIG. 10A, if the addition of the currentestimate from all of the measurements in the top stripe is expected tobe higher than the current estimate from the sum of all of themeasurements in the bottom stripe, then the area of the top strip can bemade appropriately less than the area of the bottom stripe tocompensate.

Then, each stripe can be subdivided so that the current from each cellafter division is roughly equal. This division is based on a selectedtotal number of cells for the sheet and correspondingly each stripe. Insome embodiments, estimated current for the area around each measurementpoint can be assumed approximately constant around this point.Alternatively, the estimated current at each measurement point can beextrapolated or interpolated using a linear or nonlinear algorithm. Thestripe size can be taken into account. Then, the estimated current fromeach cell in the stripe is obtained from the total estimated currentdivided by the total number of cells in a stripe. Then, the area of eachcell can be determined to yield the target current. A representativedivision into 10 cells 232 is shown in FIG. 10A.

The sheet following cutting into the 10 cells 232 is shown in FIG. 10Bwith a substrate 234 supporting the cut cells. FIG. 10B also showspositioning for doped domains 236 in which the doped domain positionsare dynamically selected so that the positions are not on a rectangulargrid. In alternative, the doped contacts can be placed on a rectangulargrid. In the embodiment shown in FIG. 10B, each vertical, but notnecessarily straight, row is selected to receive the same dopant so thatcontacts can be formed along a row.

The number and placement of the doped domains for the doping process canbe determined once the cell size is determined. Selection of dopeddomain placement can be based on keeping the number of doped domainsconstant within a cell and placing the doped domains in a particularcell based on the actual size of the cell to approximately evenly spacethe doped domains according to a selected pattern. Alternatively, thespacing between the doped domains can be targeted at a fixed value, andthe doped domains are then placed accordingly by fitting the most dopeddomains according to the space available in the cell based on the targetspacing and size of the doped domains.

Another embodiment is shown in FIG. 11 after cutting the semiconductorsheet into individual cell. In this embodiment, the sheet is cut intofive roughly equal sized rows 240, 242, 244, 246, 248. Then, each row iscut into appropriately sized cells based on measurements of thesemiconductor properties. As noted above, the number of cells generallycan be selected based on target module performance, such as based on atarget voltage. In general, a photovoltaic module can comprise, forexample, from 2 to 2000 solar cells, and in other embodiments from 10 to500 solar cells, as well as any ranges within these explicit ranges.Generally, the layout can be based on first a division into rows as inthe examples above, or the division can be any number of mathematicalalgorithms that improve current matching, such as an iterative processthat starts with equal area cells and shifts area to compensate forcurrent differences, with this correction process continuing until thecurrents are estimated to be equal within a specified tolerance.

The semiconductor sheet is further processed to form the solar cellthrough the formation of doped contacts to harvest the photocurrent andthe placement of current collectors to direct the harvestedphotocurrent. In embodiments of particular interest, the individualsolar cells are cut from a larger semiconductor sheet. The solar cellscan be positioned to receive light through a transparent front sheet.The discussion herein focuses on the formation of rear contact solarcells, but the processing can be generalized for other doped contactplacement based on the teachings herein. The cell structure processing196 (FIG. 9) can comprise, for example, one or more of the steps in FIG.12, although the steps are not necessarily performed in the orderpresented when not necessary for processing considerations, andgenerally additional processing steps can be included for specificcommercial designs. Furthermore, some of the steps of the cell structureprocessing 196 can be done prior to or concurrently in parallel withsteps relating to semiconductor measurement 192 and/or dynamic celldesign 194 of FIG. 9.

In general, referring to FIG. 12, cell structure processing 196 cancomprise, for example, depositing one or more additional layers 260,transferring the semiconductor to the transparent front sheet 262,cutting cells 264, preparing the structure for dopant deposition 266,depositing dopant composition 268, curing the dopant 270, depositingcell current collectors 272 and curing the current collectors 274,although additional steps can be used, and some steps may be combinableor optional. The deposition of additional layers can involve theformation of, for example, passivation layers along the top and/orbottom surface of the semiconductor sheet. In alternative embodiments,one or more passivation layer can be formed during the process forforming the semiconductor layer. Compositions, parameters and methodsfor forming passivation layers are described above. Additionalprotective layers, adhesive layers and processing layers can also bedeposited, which can be temporary or layers for the finished solar cell.

The passivation layers for the respective sides of the semiconductorlayer can be deposited at appropriate times in the process. Thepassivation layers are generally textured. The texturing can be donewith plasma etching or other suitable method, and/or the texture can beincorporated into the layer during deposition. Additional layers can bedeposited as appropriate to form desired structures, such as layeredcurrent collectors. Similarly, etching processes and lithographic andphotolithographic approaches can be used to pattern layers.

With respect to the transfer of the semiconductor sheet to thetransparent front sheet 262, this process depends to a significantdegree on the nature of the semiconductor. In general, this process canbe performed for thicker semiconductor structures straightforwardly. Forthin silicon foils, this process can be directly performed from astructure involving a porous, particulate release layer or priortransfer steps can be performed so that the transfer to the transparentfront sheet can take place from a temporary receiving surface. Processesand apparatus for the handling and transfer of thin inorganic foils isdescribed further in copending U.S. provisional patent application61/062,399 filed on Jan. 25, 2008 to Mosso et al., entitled “LayerTransfer for Large Area Inorganic Foils,” incorporated herein byreference. The semiconducting structure with any passivation layers andthe like can be laminated to the transparent front sheet with atransparent adhesive or the like.

Using the measurements of semiconductor properties across thesemiconductor sheet, the cells can be laid out on the sheet based ondynamic cell design discussed above. The cells are cut 264 from thesemiconductor sheet at an appropriate point in the cell structureprocessing process. Generally, the sheet is cut into cells at some pointafter measurement of the semiconductor and before final processing stepsto form the complete module. Additionally, the solar cells can be cutfrom the semiconductor sheet before or after positioning on thetransparent front sheet. Cutting after placement on the transparentfront sheet eliminates any separate alignment steps, but this processingorder generally more or less fixes the particular arrangement of thecells unless additional removal and replacement steps are performed.With the semiconductor structure for the cell in position on thetransparent substrate, additional processing can be performed on theback side of the cell until the cells are completed and integrated intothe module.

The solar cells can be cut from the semiconductor sheet based on theselected division that generally is mapped during the dynamic celldesign. The cells can be cut using reasonable mechanical methods, suchas with a saw having a hard edge blade, a fluid jet cutting apparatus orother mechanical methods. However, available laser cutting techniquesprovide for particular convenience especially with the real timedetermination of cell placement. Suitable laser cutting systems areavailable from Oxford Lasers, Inc., Shirley, Mass., USA, and IPGPhotonics Corp., Oxford, Mass., USA as well as other commercial sources.In general, any reasonable laser frequency can be used that oblates thematerial, such as Ytterbium lasers operating at 1070 nm. If thesemiconductor sheet is cut while adhered to the transparent substrate,the selected cutting approach may cut into the transparent substrateslightly without damaging cell performance as long as the transparentsubstrate maintains its mechanical integrity. In general, the lasercutting of the cells can be performed before, after or between stepsrelating to formation of the doped contacts.

The preparation for dopant deposition 266, if performed, generallyinvolves providing access to the semiconductor surface with respect topassivation layers or other layers that can be placed along thesemiconductor surface along with the dopant. In some embodiments, apassivation layer can be patterned to provide exposed regions that canaccept dopant. Photolithographic techniques, other lithographictechniques, which can involve various etching approaches, can be usedfor patterning of the structure. In principle, the patterning of thepassivation layer or other covering layers can performed after thedoping process if the dopants can be placed without migration, althoughthis processing order of doping first provides constraints on the otherprocessing steps and involves fairly precise relative positioning toproperly expose the resulting dopants. In some embodiments, a desirableapproach comprises the drilling of holes through a passivation layer.The dopants can be printed into the holes, which become the location ofthe doped contacts. The reference to holes is not intended to implycylindrical structures, and holes can have selected shapes and sizes.Appropriate ranges of hole dimensions are discussed above.

Appropriate positions for dopant deposition can be determineddynamically within each cell as described above. Holes through apassivation layer can be laser drilled or mechanically drilled. Forexample, laser hole drilling can use a green to UV laser can be usedwith a short pulse from 10 nanoseconds (ns) to 100 ns, although otherlaser frequencies and firing sequences can be used. Shorter wavelengthsand shorter pulse times are expected to cause less damage to theunderlying silicon, but there may be a range of tradeoffs from acommercial perspective, such as cost.

The laser drilling of the holes is expected to create some debris. Ashallow silicon etch can remove the debris as well as a damaged layer inthe silicon. Suitable chemical etching can be performed withnitric/hydrofluoric acid mixtures, tetramethyl-ammonium hydroxide (TMAH)or potassium hydroxide (KOH) etching compositions. In some embodiments,after the laser ablation and chemical etch, about 1% to about 50%, infurther embodiments from about 5% to about 30% and in additionalembodiments about 10% to about 25% of the dielectric passivation layeris removed to expose clean, effectively undamaged silicon underneath theholes with the remaining portions being covered by the passivationlayer. A person of ordinary skill in the art will recognize thatadditional ranges of passivation layer removal within the explicitranges above are contemplated and are within the present disclosure.

A dopant composition can then be applied through the holes to contactthe exposed silicon. In some embodiments, the dopant is delivered in adopant carrying ink, which can be dispensed, for example, using aninkjet printer of the like. Inkjet resolution over large areas ispresently readily available at 200 to 800 dpi, which is adequate topattern 100 to 200 pitch lines with single drops to cover the laserscribed holes. Also, inkjet resolution is continuing to improve. Twoinks generally are used, with one ink providing n-type dopants, such asphosphorous and/or arsenic, and the second ink providing p-type dopants,such as boron, aluminum and/or gallium. Suitable inks are describedabove that can comprise a dopant composition as a liquid or dissolved ina liquid, or comprising dopant particles, such as doped silica particlesor doped silicon particles.

After the dopant is deposited, the dopant can be cured 270 (FIG. 12) asappropriate to provide desired electrical interaction between the dopedcontact and the semiconductor material. For example, after depositingthe dopant inks, an optional drying step can be used to remove solventsand/or other organics. In some embodiments, a thin film with a thicknessof less than a micron can be left for further dopant cure processing.The nature of the dopant cure depends on the nature of the dopantcomposition. For dopant comprising liquids and silica particle inks, thedopant is driven into the silicon layer to form the doped contacts,while for silicon particle inks, the silicon can be fused in place toform the doped contacts.

For appropriate embodiments, during the drive-in step, the depositeddopant element is driven into the silicon to form a doped contact in thesilicon. The drive-in can be performed with heating in an oven toaccelerate solid state diffusion. Thermal drive-in of dopants generallyresults in a Gaussian profile of dopant in the silicon so that arelatively deep dopant structure generally is obtained to obtain adesired overall doping level. Generally, the dopant levels can be fromabout 5.0×10¹⁸ to about 5×10¹⁹ atoms per cubic centimeter (cc).

However, in some embodiments, a laser drive-in is performed, forexample, with a UV laser, such as an excimer laser, although a widerange of laser frequencies can be suitable for the laser-based dopantdrive in. In particular, excimer laser pulses of 10 to 1000 ns canresult in melting of silicon at temperatures exceeding 1400° C. todepths of 20 to 80 nm. As a specific example, excimer laser fluences ofabout 0.75 J/cm² for a 20 ns pulse or 1.8 J/cm² for a 200 ns pulse aresuitable parameters for molten regions, although other lasers, laserfrequencies and other power parameters can be used as appropriate.Dopants in the overlayer diffuse rapidly into the melted silicon, butgenerally diffuse very little past the melted silicon. Thus, anapproximately step-wise dopant profile can be achieved with dopantconcentrations possibly reaching levels greater than solubility.Additionally, the bulk of the silicon layer and lower layers remain ator near ambient room temperature, and a lower temperature process can beadvantageous since less energy is consumed.

In some embodiment, with a laser based drive in, a heavily doped contactcan be formed with a relatively shallow profile, with thickness fromabout 20 nm to about 500 nm. In some embodiments with a shallow profile,the dopant profile has at least about 95 atomic percent of the dopant inthe semiconductor within about 500 nm of the semiconductor surface andin further embodiments within about 100 nm of the semiconductor surface.The dopant profile can be measured using Secondary Ion Mass Spectrometry(SIMS) to evaluate the elemental composition along with sputtering orother etching to sample different depths from the surface.

Similarly, a doped-silicon deposit on the surface of the siliconsemiconducting sheet can be melted to form a doped contact inassociation with the semiconducting sheet. The silicon particles can bemelted in an oven or the like, or by placing the structure in a lightbased heating system, such as a laser-based scanning apparatus. Again,light sources, such as lasers, with a wide range of frequencies can beadapted to cure the silicon particles into a doped contact.

Some dopant inks may leave little if any residue after drive-in. Dopantinks using doped silica (SiO₂) generally are cleaned from the surfacefollowing dopant drive-in. Residual SiO₂ and some impurities can beremoved with an HF etch.

Referring to FIG. 12, current collector materials are deposited 272 toform electrical connections with the doped contacts so that theharvested photocurrent can be guided external to the cell. Currentcollectors are formed to electrically connect the doped contacts to formtwo poles of the cell that are suitable to connection to a moduleterminal or another cell. Within a cell, the doped contacts areelectrically connected within the cell configuration, generally withparticular polarities, i.e., types of dopant contacts, connected inparallel. The deposition of the current collector material can beperformed, for example, using an inkjet to deposit metallizationmaterials directly or to deposit a conductive seed pattern forsubsequent electroplating. In some embodiments, direct deposition ofmetallization material can comprise depositing with an inkjet an inkwith a polymer-silver particle composite For electroplating basedembodiments, a seed layer can comprise any electrically conductivematerial, such as a layer of Cu, Ag, or Ni. Use of a seed layer andsubsequent electroplating is described further, for example, in U.S.Pat. No. 6,630,387 to Horii, entitled “Method for Forming Capacitor ofSemiconductor Memory Device Using Electroplating Method,” incorporatedherein by reference.

An appropriate approach for curing of the current collector material 274(FIG. 12) depends on the nature of the current collector material. Insome embodiments, the current collector material can be heated to annealmetal or other materials to form a good juncture. Polymer metal particlecomposites can be cured into a highly conductive material upon moderateheating that is effective to crosslink the polymer. Some polymercomposites can be cured with radiation.

In some embodiments, inkjet metallization can be extended to connectmultiple solar cells in series if a bridge is used to span the gapformed from cutting the cells. The bridge should be formed from anelectrically insulating filler. Suitable fillers include, for example,compliant, flexible polymers that do not introduce strains into themodule structure. Suitable polymers can be deposited usingstraightforward processes, such as extrusion, molding or the like. Theformation of a bridge and inkjet metallization over the bridgeeliminates the need for soldering cells together. Alternatively, thecells can be soldered together with copper wires or the like, or otherapproaches to form the electrical connections can be used.

Referring to FIG. 9, once the cells car completed, further processingsteps can be performed to complete module formation 198. During finalprocessing steps to complete the module, electrodes of the solar cellscan be connected in series, and other electrical connects can be formedas desired. Also, appropriate electrodes of cells at the end of theseries are connected to module terminals. Specifically, once theelectrical connections between cells are completed, the external moduleconnections can be formed, and the rear plane of the module can besealed. A backing layer can be applied to seal the rear of the cell.Since the rear sealing material does not need to be transparent, a rangeof materials and processes can be used, as discussed above. If a heatsealing film is used, the film is put in place, and the module is heatedto moderate temperatures to form the seal without affecting the othercomponents. Then, the module can be mounted into a frame as desired.

The embodiments above are intended to be illustrative and not limiting.Additional embodiments are within the claims. In addition, although thepresent invention has been described with reference to particularembodiments, those skilled in the art will recognize that changes can bemade in form and detail without departing from the spirit and scope ofthe invention. Any incorporation by reference of documents above islimited such that no subject matter is incorporated that is contrary tothe explicit disclosure herein.

1. A photovoltaic module comprising a transparent substrate and aplurality of series-connected solar cells attached to the transparentsubstrate, wherein the area of at least two cells are different fromeach other and wherein the difference in area of the cells results in abetter match of current output of the individual cells relative to cellsof equal area with the same respective photo-conversion efficiency asthe particular cells of the module.
 2. The photovoltaic module of claim1 wherein the solar cells comprise polycrystalline silicon/germanium. 3.The photovoltaic module of claim 1 wherein the solar cells comprise asilicon/germanium layer having an average thickness form about 5 micronsto about 100 microns.
 4. The photovoltaic module of claim 1 wherein theplurality of solar cells comprises at least 10 solar cells and whereinthe area of at least two of the solar cells differ from each other by atleast about 5% relative to the average area.
 5. The photovoltaic moduleof claim 1 wherein the current output of the cells under uniformillumination with sun light differ from each other by no more than about5 percent.
 6. A solar cell comprising a semiconductor sheet having afront surface configured to receive light and a rear surface oppositethe front surface, p-dopant regions and n-dopant regions located alongthe rear surface, and two electrical interconnects providingrespectively electrical contact between the p-dopant regions and then-dopant regions, wherein p-dopant regions and the n-dopant regions arenot symmetrically located along the rear surface.
 7. The solar cell ofclaim 6 wherein the semiconductor sheet comprises polycrystallinesilicon/germanium.
 8. The solar cell of claim 7 wherein thesemiconductor sheet has an average thickness from about 5 microns toabout 100 microns.
 9. The solar cell of claim 7 wherein the dopantregions comprise doped silicon/germanium extending from the rear surfaceof the sheet.
 10. The solar cell of claim 7 wherein the dopant regionscomprise dopant extending into the rear surface of the semiconductorsheet at selected locations.
 11. The solar cell of claim 6 wherein thedopant regions are on a checker board configuration with alternatingn-doped and p-doped regions wherein the squares of the checker board areunequal in size.
 12. The solar cell of claim 6 wherein the dopantregions are arranged in rows with p-doped regions within selected rowsand n-doped regions in other rows wherein the spacing of the rows, thespacing of regions within a row or both are non-uniform.
 13. The solarcell of claim 6 wherein the dopant regions are positioned within windowsthrough a dielectric layer associated with the rear surface and whereinthe respective electrical interconnect fills the windows with anelectrically conductive material while electrically connecting theappropriate dopant regions.
 14. A method for subdividing a semiconductorsheet for use as individual photovoltaic cells within a photovoltaicmodule, the method comprising cutting the semiconductor sheet intounequal area subsections based on measurements along the semiconductorsheets, wherein the measurements are correlated with expected currentgenerated for an area of the semiconductor material at the measuredlocation.
 15. The method of claim 14 wherein the semiconductor sheetcomprises polycrystalline silicon/germanium.
 16. The method of claim 14wherein the cutting is performed using a laser.
 17. The method of claim14 wherein the semiconductor sheet has a thickness from about 5 micronsto about 100 micron and wherein the cutting is performed with thesemiconductor sheet adhered to a support sheet.
 18. The method of claim14 wherein the measurement is performed optically.
 19. A method forproducing a solar cell comprising depositing dopants in association witha semiconductor layer in an un-symmetric pattern based on performancemeasurements for semiconductor layer.
 20. The method of claim 19 whereinthe semiconductor sheet comprises polycrystalline silicon/germaniumhaving an average thickness from about 5 microns to about 100 micronsand wherein p-dopants and n-dopants are deposited along a rear surfaceof the semiconductor sheet through windows in a dielectric layer. 21.The method of claim 19 wherein p-dopants and n-dopants are deposited atselected locations and wherein the dopant regions are on a checker boardconfiguration with alternating n-doped and p-doped regions wherein thesquares of the checker board are unequal in size.
 22. The method ofclaim 19 wherein p-dopants and n-dopants are deposited at selectedlocations and wherein the dopant regions are arranged in rows withp-doped regions within selected rows and n-doped regions in other rowswherein the spacing of the rows, the spacing of regions within a row orboth are non-uniform.
 23. The method of claim 20 further comprisingdepositing two current collectors respectively providing electricalconnections between p-doped regions and n-doped regions.